The invention relates to an injection-locked oscillator circuit.
Quadrature signals are used for I/Q modulation and I/Q demodulation in various applications. I/Q modulation is understood to mean that one component of the wave is “in phase” and a second component of the wave is a “quadrature” component, that is to say has a 90° phase shift with respect to the first component. I/Q modulation is an efficient way of transmitting, modulating and demodulating phase and amplitude information.
By way of example, I/Q modulation and I/Q demodulation are applied in “wireless applications”, that is to say for example in GSM mobile radio. In “wireline applications” as well, for example in the case of “Uniphy”, signals having four clock phases are used in order to multiply sample an input signal and in order to detect the data. The systems which use I/Q (de)modulation require in each case a signal, also called system clock, having a phase angle of 0°, that is to say the system clock which is “in phase”, and a system clock having a phase angle of 90°, that is to say the system clock which represents the quadrature signal.
So-called oscillator circuits, also referred to hereinafter as oscillator stage, are used for generating the system clocks. If such an oscillator circuit is used as a so-called local oscillator, it has to fulfill very stringent specifications with regard to the phase noise proceeding from it for specific applications, for example GSM mobile radio. The temporal variation of the spacings between two zero crossings, the so-called jitter, of the oscillations proceeding from the oscillator circuit, and that is to say of the system clocks, may also be regarded as equivalent to the phase noise.
Oscillator circuits are often embodied as so-called voltage controlled oscillators or VCOs.
If an oscillator circuit is used as a local oscillator for the frequency translation of a signal to be transmitted, that is to say of the information to be transmitted, then noise in the system clock of the local oscillator leads to the “dispersal” of the transmitted signal, that is to say to a deterioration in the transmission quality of the signal. As a result of this dispersal, on the one hand it becomes more difficult to unambiguously detect the transmitted signal at the receiver end, and on the other hand the further processing of the received signal is made more difficult, if not even prevented “Wireless CMOS Frequency Synthesizer Design”; J. Craninckx, M. Steyaert; Kluwer, Boston (1998); ISBN 0-7923-8138-0. It should be noted that phase noise specifications, that is to say limit values for phase noise which have to be complied with during a transmission of a signal, are application-specific. By way of example, the phase noise specifications in the case of mobile radio emerge inter alia from the spacings between adjacent frequency channels and—within the individual frequency channels—the minimum transmission power to be detected, or the maximum permitted interference power.
For cost reasons and with the aim of simultaneous integrability of analog and digital functions on one chip, the VCOs are intended to be formed in fully integrated fashion as LC oscillators “Wireless CMOS Frequency Synthesizer Design”; J. Craninckx, M. Steyaert; Kluwer, Boston (1998); ISBN 0-7923-8138-0, “The Design of Low Noise Oscillators”; A. Hajimiri, T. H. Lee; Kluwer, Boston (1999); ISBN 0-7923-8455-5 using a CMOS technology.
A CMOS LC oscillator with quadrature signal outputs in accordance with the prior art is described in “A 900-MHz CMOS LC Oscillator with Quadrature Outputs”; A. Rofourgaran et al.; IEEE Int. Solid-State Circuits Conf. (ISSCC); Dig. Tech. Papers (February 1996); pp. 392-393. The CMOS LC oscillator described in “A 900-MHz CMOS LC Oscillator with Quadrature Outputs”; A. Rofourgaran et al.; IEEE Int. Solid-State Circuits Conf. (ISSCC); Dig. Tech. Papers (February 1996); pp. 392-393 is suitable in principle for generating I/Q signals, that is to say clock signals or system clocks having a phase angle of 0° and 90°. The device described therein has a first oscillator subcircuit and a second oscillator subcircuit. The two oscillator subcircuits are coupled by means of a transistor subcircuit comprising a total of eight transistors coupled to one another.
FIG. 10 illustrates a basic circuit diagram of a differential voltage controlled oscillator comprising cross-coupled NMOS and PMOS transistors without a current source (usually a current source is often added), which may be regarded as a basis of the considerations below containing VCOs in accordance with the prior art. The VCO 1000 illustrated in FIG. 10 has an inductance 1001, which is coupled at its two ends to respectively a first node 1002 and a second node 1003. The first node 1002 is coupled to a third node 1004, which is coupled to a first output terminal 1005 of the VCO. Furthermore, the third node 1004 is coupled to a fourth node 1006. The fourth node 1006 is coupled to a first terminal of a first varactor 1007, that is to say a variable capacitance. A second terminal of the first varactor 1007 is coupled to a fifth node 1008. The fifth node 1008 is coupled to a first terminal of a second varactor 1009. Furthermore, the fifth node 1008 is coupled to a voltage source 1010, which provides a voltage serving for setting the variable capacitances of the varactors 1007 and 1009. A second terminal of the second varactor 1009 is coupled to a sixth node 1011, which sixth node 1011 is coupled to a seventh node 1012. The seventh node 1012 is coupled to a second output terminal 1013 of the VCO. Furthermore, the seventh node 1012 is coupled to the second node 1003. The two varactors 1007 and 1009 may also be formed as an individual varactor.
Above-described elements of FIG. 10 form an LC element 1014 of the VCO. Furthermore, the VCO also has a first so-called oscillator transistor subcircuit 1015 and a second oscillator transistor subcircuit 1016. The two transistor subcircuits each have two transistors cross-connected up to one another.
The first output terminal 1005 and the second output terminal 1013 represent the output terminals of the VCO, at which the output signals of the VCO are made available, the output signals being phase-shifted by 180° relative to one another.
In detail, the second oscillator transistor subcircuit 1016 from FIG. 10 is embodied as follows.
The fourth node 1006 is coupled to an eighth node 1017. The eighth node 1017 is coupled to a first source/drain terminal 1018 of a first transistor 1019. The second source/drain terminal 1020 of the first transistor 1019 is coupled to a ninth node 1021. The ninth node 1021 is coupled to a voltage source 1022, which provides the reference voltage for the VCO. The gate terminal 1023 of the first transistor 1019 is coupled to a tenth node 1024. The ninth node 1021 is furthermore coupled to a first source/drain terminal 1025 of a second transistor 1026. The second source/drain terminal 1027 of the second transistor 1026 is coupled to the tenth node 1024 and the gate terminal 1028 of the second transistor 1026 is coupled to the eighth node 1017. Furthermore, the tenth node 1024 is coupled to the sixth node 1011.
In detail, the first oscillator transistor subcircuit 1015 from FIG. 10 is embodied as follows.
The first node 1002 is coupled to an eleventh node 1040. The eleventh node 1040 is coupled to a first source/drain terminal 1029 of a third transistor 1030. The second source/drain terminal 1031 of the third transistor 1030 is coupled to a twelfth node 1032. The twelfth node 1032 is coupled to a voltage source 1033, which provides the supply voltage for the VCO. The gate terminal 1034 of the third transistor 1030 is coupled to a thirteenth node 1035. The twelfth node 1032 is furthermore coupled to a first source/drain terminal 1036 of a fourth transistor 1037. The second source/drain terminal 1038 of the fourth transistor 1037 is coupled to the thirteenth node 1035 and the gate terminal 1039 of the fourth transistor 1037 is coupled to the eleventh node 1040. Furthermore, the thirteenth node 1035 is coupled to the second node 1003.
In FIG. 10, the four transistors each additionally have a bulk terminal, the bulk terminal of the first transistor 1019 and the bulk terminal of the second transistor 1026 being coupled to the reference voltage source 1022, whereas the bulk terminal of the third transistor 1030 and the bulk terminal of the fourth transistor 1037 are coupled to the supply voltage source 1033.
Various types of couplings of a plurality of VCOs to form a so-called oscillator ring are known in the prior art, and are described briefly below. The individual VCOs of an oscillator ring are also referred to as oscillator stages. FIG. 11 symbolically illustrates an individual oscillator stage.
In the symbolic illustration, an individual oscillator stage 1100 has a first voltage supply terminal 1101, via which a supply voltage is made available to the oscillator stage 1100. Furthermore, the oscillator stage 1100 has a second voltage supply terminal 1102, via which the oscillator stage 1100 is supplied with a tuning voltage for varactors provided in the oscillator stage 1100. The oscillator stage 1100 furthermore has a third voltage supply terminal 1103, via which the oscillator stage 1100 is supplied with a reference voltage. Furthermore, the oscillator stage 1100 has two coupling inputs 1104 and 1105, which serve for making two input signals available to the oscillator stage 1100. In this case, the two input signals have a relative phase shift of 180° with respect to one another. The oscillator stage 1100 furthermore has two coupling outputs 1106 and 1107, which serve for coupling out two output signals of the oscillator stage 1100. In this case, the two output signals have a relative phase shift of 180° with respect to one another.
The coupling of a plurality of such oscillator stages is illustrated schematically in FIG. 12. In this case, the tuning voltage, reference voltage and supply voltage are identical for all the oscillator stages and the coupling of the individual voltage sources is not illustrated in FIG. 12.
In FIG. 12, three oscillator stages 1100a, 1100b and 1100c as illustrated in FIG. 11 are schematically coupled to one another. It should furthermore be noted that the individual oscillator stages, in addition to an individual so-called cross-coupling are coupled among one another by means of so-called direct couplings, that is to say that the output signal having a phase angle of 180° is applied to the input terminal having a phase angle of 180°, and the output signal having a phase angle of 0° applied to the input terminal having a phase angle of 0°. In a coupling of the individual oscillator stages, the output terminals of one oscillator stage are in each case coupled to the input terminals of the next oscillator stage.
The schematic illustration of coupled oscillator stages is described in detail below. A first output terminal 1106a of a first oscillator stage 1100a, which for example provides a signal having a phase angle of 180°, is coupled to a first input terminal 1104b of a second oscillator stage 1100b, which input terminal has a phase angle of 180°. A second output terminal 1107a of the first oscillator stage 1100a, which in the example provides a signal having a phase angle of 0°, is coupled to a second input terminal 1105b of the second oscillator stage 1100b, which input terminal has a phase angle of 0°.
Furthermore, a first output terminal 1106b of the second oscillator stage 1100b, which in the example provides a signal having a phase angle of 180°, is coupled to a first input terminal 1104c of a third oscillator stage 1100c, which input terminal has a phase angle of 180°. A second output terminal 1107b of the second oscillator stage 1100b, which in the example provides a signal having a phase angle of 0°, is coupled to a second input terminal 1105c of a third oscillator stage 1100c, which input terminal has a phase angle of 0°.
Additional oscillator stages may be coupled in the manner described previously. This is indicated in FIG. 12 by the dashed couplings illustrated between the second oscillator stage 1100b and the third oscillator stage 1100c. 
The last oscillator stage, the third oscillator stage 1100c in FIG. 12, is coupled to the first oscillator stage 1100a. It should be taken into consideration in the case of this coupling that this coupling is a cross-coupling.
In detail, the coupling of the third oscillator stage 1100c to the first oscillator stage 1100a is as follows. A first output terminal 1106c of the third oscillator stage 1100c, which in the example provides a signal having a phase angle of 180°, is coupled to a second input terminal 1105a of the third oscillator stage 1100a, which input terminal has a phase angle of 0°. A second output terminal 1107c of the third oscillator stage 1100c, which in the example provides a signal having a phase angle of 0°, is coupled to a first input terminal 1104a of the first oscillator stage 1100a, which input terminal has a phase angle of 180°.
For a stable oscillation, the phase rotation along the total number of oscillator stages, that is to say along the so-called oscillator ring, must amount to a multiple of 2π. It should furthermore be taken into consideration that when a plurality of oscillator stages are arranged in an oscillator ring the current consumption of the oscillator ring rises since there is an increased number of current paths between the supply voltage (Vdd) and the reference voltage (Vss). In this case, the rise in the current consumption is approximately linear with the number of oscillator stages used.
In principle, two possibilities for the realization of the coupling inputs in the individual oscillator stages are known. These are firstly the so-called serial coupling, which is described for example in “Analysis and Design of a 1.8 GHz CMOS LC Quadrature VCO”; P. Andreani et al.; Journal of Solid State Circuits vol. 37 No. 12 (December 2002) pp. 1737-1747 and “A 1.8 GHz CMOS Quadrature Voltage Controlled Oscillator (VCO) Using the Constant Current LC Ring Oscillator Structure”; C. J. Wu, H. S. Kao; International Symposium on Circuits and Systems (1998) pp. 378-381, and secondly the so-called parallel coupling, which is described for example in “Low Power, Low-Phase-Noise differentially tuned Quadrature VCO Design in Standard CMOS”; Tiebout M., Journal of Solid State Circuits, Vol. 36, No. 7, (July 2001) pp. 1018-1024, “Single-Chip 900 MHz Spread-Spectrum Wireless Transceiver in 1-μm CMOS—Part I: Architecture and Transmitter Design”, A. Rofourgaran et al.; Journal of Solid State Circuits, Vol. 33, No. 4, (April 1998) pp. 515-534 and “A Low-Phase-Noise CMOS LC Oscillator with a Ring structure”, J. J. Kim and B. Kim; International Solid State Circuits Conference, Vol. XLIII (February 2000) p. 430. Both types of coupling and, in particular, the corresponding configuration of the oscillator stages are explained in more detail below.
Firstly, an oscillator basic stage for a serial coupling is described with reference to FIG. 13. An inductance 1300 is coupled to a first node 1301 at a first end. The first node 1301 is coupled to a second node 1302. The second node 1302 is coupled to a first output terminal 1303. Furthermore, the second node 1302 is coupled to a third node 1304. The third node 1304 is coupled to a fourth node 1305. The fourth node 1305 is coupled to a first source/drain terminal 1306 of a first transistor 1307. The second source/drain terminal 1308 of the first transistors coupled to a first source/drain terminal 1309 of a second transistor 1310. Furthermore, a bulk terminal 1311 of the first transistor is coupled to a reference voltage source 1312. The second source/drain terminal 1313 of the second transistor 1310 is coupled to a fifth node 1314. Furthermore, a bulk terminal 1315 is coupled to the second source/drain terminal 1313 of the second transistor 1310. The fifth node 1314 is coupled to a reference voltage source 1316. The fifth node 1314 is furthermore coupled to a first source/drain terminal 1317 of a third transistor 1318 and the first source/drain terminal 1317 of the third transistor 1318 is coupled to a bulk terminal 1319 of the third transistor 1318. The second source/drain terminal 1320 of the third transistor 1318 is coupled to a first source/drain terminal 1321 of a fourth transistor 1322. The gate terminal 1323 of the third transistor 1318 is coupled to the fourth node 1305. The second source/drain terminal 1324 of the fourth transistor 1322 is coupled to a sixth node 1325. A bulk terminal 1326 of the fourth transistor 1322 is coupled to a reference voltage source 1327. The sixth node 1325 is coupled to the gate terminal 1328 of the second transistor 1310. Furthermore, the sixth node 1325 is coupled to a seventh node 1329. The seventh node 1329 is coupled to an eighth node 1330. Furthermore, the seventh node 1329 is coupled to a first terminal of a first varactor 1331. The second terminal of the first varactor 1331 is coupled to a ninth node 1332. The ninth node 1332 is coupled to a tuning voltage source 1333. Furthermore, the ninth node 1332 is coupled to a first terminal of a second varactor 1334. The second terminal of the varactor 1334 is coupled to the third node 1304.
The tuning voltage source 1333 is used to provide a voltage for tuning the capacitance for the two varactors 1331 and 1334. The two varactors may also be formed as an individual varactor. The voltages which are provided by means of the reference voltage sources 1312, 1316 and 1327 are identical in magnitude and are also designated as Vss hereinafter and in the Figures.
The eighth node 1330 is coupled to a second output terminal 1335, which provides a signal for outputting which is phase-shifted by 180° relative to the signal present at the first output terminal 1303. The eighth node 1330 is furthermore coupled to a tenth node 1336. The tenth node 1336 is coupled to the second terminal of the inductance 1300.
The tenth node 1336 is furthermore coupled to an eleventh node 1337. The eleventh node 1337 is coupled to a first source/drain terminal 1338 of a fifth transistor 1339. The second source/drain terminal 1340 of the fifth transistor 1339 is coupled to a first source/drain terminal 1341 of a sixth transistor 1342. A bulk terminal 1343 of the fifth transistor 1339 is coupled to a first supply voltage source 1344. The second source/drain terminal 1345 of the sixth transistor 1342 is coupled to a twelfth node 1346. A bulk terminal 1347 of the sixth transistor 1342 is coupled to the second source/drain terminal 1345 of the sixth transistor 1342. The twelfth node 1346 is coupled to a second supply voltage source 1368. Furthermore, the twelfth node is coupled to a first source/drain terminal 1348 of a seventh transistor 1349. The second source/drain terminal 1350 of the seventh transistor 1349 is coupled to a first source/drain terminal 1351 of an eighth transistor 1352. A bulk terminal 1353 of the seventh transistor 1349 is coupled to the first source/drain terminal 1348 of the seventh transistor 1349. The gate terminal 1354 of the seventh transistor 1349 is coupled to the eleventh node 1337. The second source/drain terminal 1355 of the eighth transistor 1352 is coupled to a thirteenth node 1356. A bulk terminal 1357 of the eighth transistor 1352 is coupled to a third supply voltage source 1358. The thirteenth node 1356 is coupled to the first node 1301. Furthermore, the thirteenth node 1356 is coupled to the gate terminal 1359 of the sixth transistor 1342.
The voltages which are provided by means of the supply voltage sources 1344, 1347 and 1358 are identical in magnitude and are also designated as Vdd hereinafter and in the Figures.
The oscillator stage and the two differential output terminals have been described above with reference to FIG. 13. However, the oscillator stage additionally also has input terminals, which are described below.
The input terminals are formed by means of the gate terminals of the first, fourth, fifth and eighth transistors. For this purpose, the gate terminal 1360 of the first transistor 1307 is coupled to a fourteenth node 1361. The fourteenth node 1361 is coupled to the gate terminal 1362 of the eighth transistor 1352. Furthermore, the fourteenth node 1361 is coupled to a first input terminal 1363. The gate terminal 1364 of the fourth transistor 1322 is coupled to a fifteenth node 1365, which fifteenth node 1365 is coupled to the gate terminal 1366 of the fifth transistor 1339. The fifteenth node 1365 is furthermore coupled to a second input terminal 1367.
In general, the first transistor, the fourth transistor, the fifth transistor and the eighth transistor represent coupling transistors of the oscillator stage, whereas the second transistor, the third transistor, the sixth transistor and the seventh transistor represent oscillator transistors of the oscillator stage.
With reference to FIG. 13, it can also be explained more precisely what is to be understood by the direct coupling already mentioned above and the cross-coupling.
By way of example, the signal at the first output terminal 1303 of a first oscillator stage has a phase angle of 180°. In the case of a direct coupling, this output signal of the first output terminal 1303 is coupled to the second input terminal 1367 of the downstream oscillator stage. The signal which is present at the second output terminal 1335 of the first oscillator stage and has a phase angle of 0° is coupled to the first input terminal 1363 of the downstream oscillator stage.
In contrast to this, the cross-coupling is embodied as follows.
By way of example, the signal at the first output terminal 1303 of a first oscillator stage has a phase angle of 180°. In the case of a cross-coupling, this output signal of the first output terminal 1303 is coupled to the first input terminal 1363 of the downstream oscillator stage. The signal which is present at the second output terminal 1335 of the first oscillator stage and has a phase angle of 0° is coupled to the second input terminal 1367 of the downstream oscillator stage.
Any arbitrary number of stages is possible in the case of serial coupling of oscillator stages. In this case, the phase difference between the successive stages is dependent on the number of stages which are present in an oscillator ring. In this case, the phase shift within the entire oscillator ring must amount to a multiple of 2π.
One disadvantage of a serial oscillator ring, however, is that, on account of the serial coupling, both the oscillator transistors and the coupling transistors must have a relatively large width in order to enable enough current through the respective active branch of the circuit, because the oscillator transistors and the coupling transistors are not in the same state. This results in high parasitic capacitances within the oscillator ring, which adversely affect the frequency tuning capability and the current consumption of the oscillator ring. An additional disadvantage is that as a result of the enlargement of the dimensions of the transistors which accompanies the relatively large widths of the transistors, there is the risk of the inherent noise of the transistors being increased, which in turn contributes to a higher phase noise of the oscillator.
An oscillator basic stage for a parallel coupling is described below with reference to FIG. 14. An inductance 1400 is coupled to a first node 1401 at a first end. The first node 1401 is coupled to a second node 1402. The second node 1402 is coupled to a first output terminal 1403. Furthermore, the second node 1402 is coupled to a third node 1404. The third node 1404 is coupled to a fourth node 1405. The fourth node 1405 is coupled to a fifth node 1406. The fifth node 1406 is coupled to a first source/drain terminal 1407 of a first transistor 1408. The second source/drain terminal 1409 of the first transistor 1408 is coupled to a sixth node 1410. Furthermore, a bulk terminal 1411 of the first transistor 1408 is coupled to a seventh node 1412. The seventh node 1412 is coupled to the sixth node 1410. The sixth node 1410 is furthermore coupled to an eighth node 1413. The eighth node 1413 is coupled to a reference voltage source 1414. The eighth node 1413 is furthermore coupled to a ninth node 1415, which is coupled to a first source/drain terminal 1416 of a second transistor 1417. Furthermore, the ninth node 1415 is coupled to a bulk terminal 1418 of the second transistor 1417. The second source/drain terminal 1419 of the second transistor 1417 is coupled to a tenth node 1420. The tenth node 1420 is coupled to an eleventh node 1421. The eleventh node 1421 is coupled to a twelfth node 1422.
Furthermore, the eleventh node 1421 is coupled to the gate terminal 1423 of the first transistor 1408 and the gate terminal 1424 of the second transistor 1417 is coupled to the fourth node 1405.
The twelfth node 1422 is coupled to a thirteenth node 1425. Furthermore, the twelfth node 1422 is coupled to a first terminal of a first varactor 1471. The second terminal of the first varactor 1471 is coupled to a fourteenth node 1426. The fourteenth node 1424 is coupled to a tuning voltage source 1427. Furthermore, the fourteenth node 1426 is coupled to a first terminal of a second varactor 1428. The second terminal of the varactor 1428 is coupled to the third node 1404.
The two varactors 1471 and 1428 may also be formed as one individual varactor.
The thirteenth node 1425 is coupled to a fifteenth node 1429. Furthermore, the thirteenth node 1425 is coupled to a second output terminal 1430. The fifteenth node 1429 is coupled to a sixteenth node 1431 and furthermore to the second terminal of the inductance 1400.
The sixteenth node 1431 is coupled to a third source/drain terminal 1432 of a third transistor 1433. The second source/drain terminal 1434 of the first transistor 1433 is coupled to a seventeenth node 1435. Furthermore, a bulk terminal 1436 of the third transistor 1433 is coupled to an eighteenth node 1437. The eighteenth node 1437 is coupled to the seventeenth node 1435. The seventeenth node 1435 is furthermore coupled to a nineteenth node 1438. The nineteenth node 1438 is coupled to a supply voltage source 1439. The nineteenth node 1438 is furthermore coupled to a twentieth node 1440, which is coupled to a first source/drain terminal 1441 of a fourth transistor 1442. Furthermore, the twentieth node 1440 is coupled to a bulk terminal 1443 of the fourth transistor 1442. The second source/drain terminal 1444 of the fourth transistor 1442 is coupled to the twenty-first node 1445. The twenty-first node 1445 is coupled to a twenty-second node 1446. The twenty-second node 1446 is coupled to the first node 1401.
Furthermore, the twenty-second node 1446 is coupled to the gate terminal 1447 of the third transistor 1433 and the gate terminal 1448 of the fourth transistor 1442 is coupled to the sixteenth node 1431.
The oscillator stage and the two differential output terminals have been described above with reference to FIG. 14. However, the oscillator stage additionally also has input terminals, which are described below.
The input terminals are formed by means of the gate terminals of four additional transistors which are connected in parallel with the first four transistors.
The fifth node 1406 is coupled to a first source/drain terminal 1449 of a fifth transistor 1450. The second source/drain terminal 1451 of the fifth transistor 1450 is coupled to the sixth node 1410. A bulk terminal 1472 of the fifth transistor 1450 is coupled to the seventh node 1412. The gate terminal 1452 of the fifth transistor 1450 is coupled to a twenty-third node 1453. The twenty-third node 1453 is coupled to a first input terminal 1454. Furthermore, the twenty-third node 1453 is coupled to the gate terminal 1455 of a sixth transistor 1456. A first source/drain terminal 1457 of the sixth transistor 1456 is coupled to the twenty-first node 1445. The second source/drain terminal 1458 of the sixth transistor 1456 is coupled to the twentieth node 1440. Furthermore, a bulk terminal 1459 of the sixth transistor 1456 is coupled to the twentieth node 1440.
The tenth node 1420 is coupled to a first source/drain terminal 1460 of a seventh transistor 1461. The second source/drain terminal 1462 of the seventh transistor 1461 is coupled to the ninth node 1415. A bulk terminal 1473 of the seventh transistor 1461 is coupled to the ninth node 1415. The gate terminal 1463 of the seventh transistor 1461 is coupled to a twenty-fourth node 1464. The twenty-fourth node 1464 is coupled to a second input terminal 1465. Furthermore, the twenty-fourth node 1454 is coupled to the gate terminal 1466 of an eighth transistor 1467. A first source/drain terminal 1468 of the eighth transistor 1467 is coupled to the sixteen node 1431. The second source/drain terminal 1469 of the eighth transistor 1467 is coupled to the seventeenth node 1435. Furthermore, a bulk terminal 1470 of the eighth transistor 1467 is coupled to the eighteenth node 1427.
In general, the first transistor, the second transistor, the third transistor and the fourth transistor represent oscillation transistors of the oscillator stage, whereas the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor represent coupling transistor of the oscillator stage.
With reference to FIG. 14, it can likewise be explained more precisely what is to be understood by the direct coupling already mentioned above and the cross-coupling.
By way of example, the signal at the first output terminal 1403 of a first oscillator stage has a phase angle of 180°. In the case of a direct coupling, this output signal of the first output terminal 1403 is coupled to the second input terminal 1465 of the downstream oscillator stage. The signal which is present at the second output terminal 1430 of the first oscillator stage and has a phase angle of 0° is coupled to the first input terminal 1454 of the downstream oscillator stage.
In contrast to this, the cross-coupling is embodied as follows.
By way of example, the signal at the first output terminal 1403 of a first oscillator stage has a phase angle of 180°. In the case of a cross-coupling this output signal of the first output terminal 1403 is coupled to the first input terminal 1454 of the downstream oscillator stage. The signal which is present at the second output terminal 1430 of the first oscillator stage and has a phase angle of 0° is coupled to the second input terminal 1465 of the downstream oscillator stage.
Any arbitrary number of stages is possible in the case of a parallel coupling of oscillator stages. In this case, the phase difference between the successive stages is dependent on the number of stages which are present in an oscillator ring; by way of example, with the use of two oscillator stages, the signals are in quadrature since a phase rotation of ±90° results.
By means of a parallel coupling of oscillator stages, in comparison with the serial coupling smaller widths both of the oscillation oscillators and of the coupling oscillators are possible since the currents are cumulated in the case of the parallel circuit respectively comprising two transistors as illustrated in FIG. 14. As a result, the varactor that is required to enable a predetermined frequency range to be covered can likewise be reduced in size. This in turn permits the inductance to be enlarged and hence an additional reduction both of the phase noise and of the current consumption of the oscillator ring with parallel coupling of the oscillator stages.
By means of a parallel coupling of oscillator stages, in comparison with single-stage oscillators with a corresponding basic cell, that is to say a basic cell as illustrated in FIG. 10, a reduction of the phase noise is possible according to simulation calculations. For an oscillator ring comprising two oscillator stages connected in parallel, a reduction of the phase noise by up to 7 dBc is produced in simulations at an oscillator frequency of between 3.0 GHz and 4.2 GHz. For an oscillator ring comprising four oscillator stages connected in parallel, a reduction of the phase noise by about 8 dBc/Hz, where dBc means “dB with respect to carrier power”, is produced in simulations at an oscillator frequency of between 3.0 GHz and 4.2 GHz compared with an oscillator ring comprising two oscillator stages connected in parallel.
Compared with serial coupling, a parallel coupling of the individual oscillator stages, given a number of four oscillator stages, exhibits an improvement of up to 8 dBc/Hz according to simulations.
A significant disadvantage of the parallel coupling of oscillator stages to form an oscillator ring is that it has been found that a plurality of oscillator states are possible. As a result of this, some specimens of oscillator rings with parallel coupling have clock signals having a phase angle of 0° and −90° instead of clock signals having a phase angle of 0° and +90°. These two different “types” of oscillator rings then also have a different value for the phase noise. Consequently, the oscillator rings comprising oscillator stages coupled in parallel cannot be used without problems for generating two clock signals having a fixed, predeterminable phase angle.
In addition, the devices in accordance with the prior art have overall complicated interconnection.
Furthermore, U.S. Pat. No. 6,417,740 B1 discloses a signal generator for a variable frequency, which is formed as a voltage controlled oscillator circuit and which has broadband and/or multiband frequency output function and uses two control voltages.
U.S. Pat. No. 6,198,360 B1 discloses a circuit and a method used in LC or ring oscillators, the frequency of the oscillation being modulated by means of detecting a quadrature signal and by means of controlling the sign and the strength of the quadrature signal.
U.S. Pat. No. 6,617,936 B2 discloses an oscillator circuit which achieves the phase-shifting of an oscillating signal toward the phase of an input signal coupled to the oscillating signal.